FIELD: computing technology.
SUBSTANCE: technical result is achieved due to the known apparatus, containing a first shift register, a second shift register, a permutation generation unit, a permanent memory unit, a best option storage unit, a switch, an arithmetic logic apparatus, an arc selection decoder, a reversible cell counter, a RAM unit, a first comparison element, a count start trigger, a mode trigger, an arc counter, an arc locking decoder, an arc number register, a minimum weight register, an electronic graph model, a group of OR elements, a group of AND elements, and a first delay element, including a minimum value search unit containing a group of adders, a first group of vertex number registers, a second group of vertex number registers, a group of mode triggers, a group of delay elements, a vertex selection decoder, a vertex number counter, a block of OR elements, and a minimum value adder.
EFFECT: ensured detection of the minimum value of placement intensity in multiprocessor hypercubic systems based on the criterion of minimising the intensity of process and data interaction.
2 cl, 8 dwg
