FIELD: physics, computer engineering.
SUBSTANCE: invention relates to digital computer engineering and is meant for simulating combinatorial problems when designing computer systems, e.g., for deploying processes (tasks, files, data, control processes etc.). The device has shift registers, a shift generating unit, a read-only memory unit, a best version storage unit, a switch, an arithmetic logic unit (ALU), decoders, a bidirectional cell counter, a random-access memory unit, counters, a multiplier, an adder, registers, comparing elements, a subtractor, flip-flops, an electronic graph model, a group of OR elements, a group of AND elements, AND elements, OR element units, univibrators, delay elements, a lower bound generating unit, having an array of adders, row counters, column counters, an array of registers, decoders of horizontally fixed arcs, decoders of vertically fixed arcs, an array of OR elements, arrays of AND elements, OR elements, an RS flip-flop and an incident vertex counter.
EFFECT: wider field of using the device owing to inclusion of location lower-bound estimate search devices in fully connected matrix systems during one-way data transfer based on the criterion for minimising intensity of interaction of processes and data.
2 cl, 7 dwg
