FIELD: information technology.
SUBSTANCE: device has a shift register, wherein the bit of the shift register includes an asynchronous RS flip-flop, which is configured to receive an initialisation signal, and a signal generating circuit which is configured to receive a simultaneous selection signal, wherein the signal generating circuit is configured to generate an output bit signal through the output signal of the flip-flop; the output bit signal becomes active under the action of the simultaneous selection signal and then stored active during simultaneous selection; the output signal of the flip-flop is inactive when the initialisation signal is active irrespective of whether each of the set signal and the reset signal is active or inactive; and the initialisation signal becomes active before the end of simultaneous selection and becomes inactive after the end of simultaneous selection.
EFFECT: providing stable operation of a shift register after the end of simultaneous selection of a plurality of signalling lines, carried out by a display driver circuit at given moments in time.
24 cl, 43 dwg
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Authors
Dates
2013-07-10—Published
2010-03-18—Filed