FIELD: information technology.
SUBSTANCE: disclosed is a display panel driving circuit comprising a shift register, with which unit circuits for generating signal line selecting signals (G1-Gm) are stepwise connected, for outputting pulses formed from the signal line selecting signals (G1-Gm), sequentially from an initial stage to a final stage. To each of the unit circuits, there are inputted clock signals (CK1 and CK2), either a gate start pulse signal (GSP) generated on the basis of a synchronising signal (VSYNC) from the outside of the display panel driving circuit or the signal line selecting signals (G1-Gm) generated at another stage, and a clear signal (CLR). The clear signal (CLR) is activated in the case where the synchronising signal (VSYNC) is abnormal, and no pulse is subsequently outputted from the shift register till the start of the next vertical scanning period.
EFFECT: broader functional capabilities, particularly preventing disruption of display and increasing load on the power supply.
36 cl, 42 dwg
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Authors
Dates
2012-07-10—Published
2008-12-17—Filed