RESTRICTING MEMORY AREAS FOR INSTRUCTION READING DEPENDING ON HARDWARE MODE AND SECURITY FLAG Russian patent published in 2014 - IPC G06F21/74 G06F9/312 

FIELD: physics, computer engineering.

SUBSTANCE: invention relates to data processing systems, having a plurality of operating hardware modes, and managing memory access depending on the current hardware mode. An apparatus for processing data (2) includes a processor (8), a memory (6) and memory control circuit (12). The processor (8) operates in a plurality of hardware modes including a privileged mode and a user mode. When operating in the privileged mode, the processor (8) is blocked by the memory control circuit (12) from fetching instructions from memory address regions (34, 38, 42) within the memory (6) which are writeable within the user mode if a security flag within register (46) is set to indicate that this blocking mechanism is active.

EFFECT: enabling a processor to access data in memory even when that option is blocked in the current operating mode of the processor.

13 cl, 4 dwg