FIELD: radio engineering, communication.
SUBSTANCE: network adapter includes a programmable logic device and PCIe and QSFP+ sockets. The programmable logic device includes injectors designed to receive PCIe packets from a processor and generate messages therefrom, ejectors designed to receive messages and generate PCIe packets therefrom, a router and transceivers. The injector writes incoming PCIe packets in a ring buffer, where cell padding is counted. When a cell, having a message header and a payload data origin, and all the other cells required to generate a message are completely filled, the injector extracts from said cells the message header and the payload data and generates a message. For each received message, the ejector generates one PCIe packet measuring 64-256 bytes depending on the size of the message. The size of the PCIe packet is a multiple of 64 and the packet includes payload data, unused data and a message header containing a parity bit. The message header is always situated at a known place and always arrives at the processor later than the payload data.
EFFECT: increasing real throughput and reducing delay when exchanging messages measuring 56 to 248 bytes via a PCIe bus between a network adapter and a processor of a computational node.
2 cl, 6 dwg
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Authors
Dates
2016-02-10—Published
2014-10-15—Filed