FIELD: information technology.
SUBSTANCE: there is the first data structure including a plurality of the physical register values; the second data structure including a plurality of the reference elements for pointers to the first data structure; the third data structure including a plurality of the removal deletion sets, wherein each removal deletion set comprises two or more bits representing two or more logical data registers; the third data structure further comprises, at least, one bit associated with each removal deletion set, and, at least, one bit representing one or more logical flag registers; the fourth data structure including a data register identifier sharing an element of the first data structure with the flag register; and the logical removal deletion scheme is configured to perform the removal deletion operation.
EFFECT: improving the overall processor performance.
17 cl, 24 dwg
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