INSTRUCTION AND LOGIC FOR MEMORY ACCESS IN A CLUSTERED WIDE-EXECUTION MACHINE Russian patent published in 2018 - IPC G06F12/802 G06F12/84 

FIELD: data processing.

SUBSTANCE: group of inventions refers to the field of information processing logic. Processor includes a level-2 cache (L2), the first and second cluster of execution units and the first and second data cache unit (DCU) coupled to the capability of communication with the respective clusters of execution units and the L2 cache, each of the DCUs includes a data cache and logic for receiving a memory operation from the execution unit, response to a memory operation with information from the data cache when the information is available in the data cache, and extracting information from the L2 cache when information is not available in the data cache. Processor further includes logic to maintain the data cache of the first DCU to the content of the data cache of the second DCU in all clock cycles of the processor.

EFFECT: increased productivity.

20 cl, 31 dwg