DISPLAY OF IMBEDDED ADDRESS OF ECC Russian patent published in 2018 - IPC G06F11/10 G06F12/02 

FIELD: information technology.

SUBSTANCE: device comprises a processor and a memory management logic configured to receive a request for access to data in the storage device. The data is displayed to a page of memory containing a number of cache lines; shifting at least a portion of the plurality of rows of the cache for embedding error correction code (ECC) in the information data; repeated display of the said part from a plurality of cache lines to another location in memory and accessing data and ECC information on a page of memory, wherein the storage device is divided into a plurality of partial arrays; the write request is directed to the selected partial array, a logic circuit configured to re-display the part of the plurality of cache lines to a predetermined location in the selected partial array, said partial array further comprising said ECC information. The specified location corresponds to the top of the specified partial array.

EFFECT: saving energy and reducing the delay in access to data.

18 cl, 12 dwg