DELAYED CLEARING OF TRANSLATION LOOKASIDE BUFFERS Russian patent published in 2009 - IPC G06F12/00 G06F9/32 G06F9/04 

FIELD: physics; computer engineering.

SUBSTANCE: invention pertains to memory control, more specifically to clearing address translation cache-buffers. Address translation control (ATC) limits imagery between virtual and physical addresses, so as to implement the memory access policy. Each processor in a multiprocessor system supports a translation lookaside buffer (TLB), which caches imagery to speed up translation of virtual addresses. Each processor also supports a counter. Each time the TLB of a processor is cleared, the processor counter increases. When a link on page is deleted from the address translation map, the counter value for all processors is recorded. When the processor accesses the page, the recorded counter values are compared with the current counter value of the processor to determine whether the processor TLB has been cleared since the link on the page was deleted from the map. The costly operation of clearing TLB is delayed until it is required, but, it is however done in time to prevent use of invalid records in TLB to violate access policy.

EFFECT: increase of functional capabilities.

11 cl, 6 dwg