DEVICE FOR READING SIGNALS FROM A PHOTODETECTOR MATRIX OF INFRARED RADIATION (VERSIONS) Russian patent published in 2019 - IPC H01L27/14 

FIELD: data processing.

SUBSTANCE: invention can be used for processing optical information. Essence of the invention consists in that the device for reading signals from the photodetector matrix of infrared radiation comprises an input cell with a capacitive transimpedance amplifier with inverting and non-inverting inputs, made on the basis of the operational amplifier with a storage capacitor connected in parallel to the negative feedback circuit, a column bus, column charge-sensitive amplifier with a second operational amplifier and connected in parallel to the negative feedback circuit by a capacitor, further comprises a second column bus, wherein one column bus is realized in the form of a signal column bus, and second column bus is implemented in the form of reference column bus, capacitive transimpedance amplifier is also made with input inclusion, in composition of input cell also made integrating transistor, reset transistor, first and second address transistors, integrating start transistor is connected by its source to inverting input of capacitance transimpedance amplifier, which is inverting input of operational amplifier, and the first capacitor capacitor cap, by its drain the integration start transistor is connected to the photodiode cathode, the gate of the integrating start transistor is connected to the input input of the capacitive trans-impedance amplifier, which is the input input of the operational amplifier, wherein said gate and input are configured to supply a control signal of the beginning of integration, the discharge transistor by its drain is connected to the source of the integrating transistor and the first capacitor capacitor plate, by the reset source, the reset transistor is connected to the output of the capacitive trans-impedance amplifier, which is the output of the operational amplifier, and a second capacitor capacitor plate, the resetting transistor gate is configured to supply an input cell reset signal thereto, first address transistor by its drain is connected to inverting input of capacitive transimpedance amplifier, which is inverting input of operational amplifier, first capacitor capacitor coating, source of transistor of integration beginning, drain of reset transistor, source of first address transistor is connected to signal column bus, gate of the first address transistor is connected to the gate of the second address transistor, wherein gates of the first and second address transistors are configured to supply a reading signal thereto, second address transistor by its drain is connected to output of capacitive trans-impedance amplifier, which is output of operational amplifier, with a second capacitor capacitor coating, with a resetting transistor source, and the second address transistor source source is connected to the reference column bus, non-inverting input of the capacitive trans-impedance amplifier, which is a non-inverting input of the operational amplifier, is configured to apply a reference voltage thereto, as a part of the charge-sensitive column amplifier, a second reset transistor is made, wherein the charge-sensitive column amplifier is provided with inverting and non-inverting inputs, respectively inverting and non-inverting inputs of the second operational amplifier, non-inverting input of the column charge-sensitive amplifier is connected to a reference column bus configured to supply a reference voltage thereto, inverting input of a column charge-sensitive amplifier is connected to a first electrode of a capacitor connected in parallel to a negative feedback circuit in the form of a linear capacitor with a discrete set of capacitance values, with a signal column bus, with a drain of the second reset transistor, source of the second reset transistor is connected to the second electrode of the capacitor connected in parallel to the negative feedback circuit in the form of a linear capacitor with a discrete set of capacitance values, with the output of the column charge-sensitive amplifier, which is the output of the second operational amplifier, and the gate of the second reset transistor is configured to supply a reset signal of the column charge-sensitive amplifier to it.

EFFECT: possibility of reducing power consumption, improving homogeneity of the output signal.

5 cl, 4 dwg