FIELD: data processing.
SUBSTANCE: device belongs to the field of integrated microelectronics, it is intended for processing of optical information. Device is characterized by a multi-channel reading system within the matrix of reading cells. Reading cell contains a capacitive trans-impedance amplifier with an integrating capacitance, high-pass filter, comparator, time-to-voltage converter, logic unit, N-bit counter, M-bit memory circuit. Capacitive trans-impedance amplifier is connected by one of the inputs to the photo diode, it is configured to reset the integrating capacitance. Capacitive trans-impedance amplifier output is connected to a high-pass filter. High-pass filter output is connected through a switch to a comparator inverting input. Comparator inverting input is also connected via another switch to the time to voltage converter output. Comparator output is connected to the first input of the logic block. Logic unit first output is connected to the input of the time to voltage converter. Logic block second input is intended to provide a signal that determines device operation mode. Logic unit second output is connected to a capacitive trans-impedance amplifier to reset the integrating capacitance. Logic unit third input is supplied with a signal that determines the counter operating mode. Logic unit third output is connected to the N-bit counter counting input. Logic unit fourth input is supplied with a signal to reset the counter. Logic unit fifth input is supplied with the generated clock pulses. Time to voltage converter is made with two inputs and one output. One of the inputs is supplied with a signal from the logic unit. Second input is supplied with a signal from the sawtooth generator. Output is connected to the comparator inverting input through a key. N-bit counter is made with two inputs and one output. Its first input is supplied with a signal to reset the counter. Second, countable, input is connected to the logic unit third output. N-bit counter output is connected to the input of the M-bit memory circuit. Second and third inputs are connected to the column read and write buses, respectively. M-bit memory circuit output is connected to the lower-order output bus of the N output.
EFFECT: as a result, the spatial resolution is improved and the power consumption is reduced when operating in two modes - thermal imagery generation and three-dimensional imagery generation.
13 cl, 11 dwg
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Authors
Dates
2018-02-21—Published
2016-12-06—Filed