FIELD: computing technology.
SUBSTANCE: disclosed is an arithmetic unit modulo three, containing three AND elements, two EXCLUSIVE-OR elements and two OR elements, wherein two EXCLUSIVE-OR elements and two OR elements are additionally introduced thereto, wherein the first, second inputs of the first and the first, second inputs of the second OR elements are connected with the second inputs of the second, first EXCLUSIVE-OR elements and the first inputs of the fourth, third OR elements, respectively, the first, second inputs of the jth and the first, second inputs of the third AND elements are connected with the outputs of the jth EXCLUSIVE-OR element, the first OR element and the outputs of the first, second OR elements, respectively, the second input of the (j+2)th OR element and the first, second inputs of the (j+2)th EXCLUSIVE-OR element are connected with the output of the jth AND element and the outputs of the (j+2)th OR element, the third AND element, respectively, and the first input of the (j+2)th OR element and the second input of the jth EXCLUSIVE-OR element are connected with the jth and (j+2)th information inputs of the arithmetic unit modulo three, respectively, wherein the configuration input and the jth output of said unit are connected with the first input of the jth and the output of the (j+2)th EXCLUSIVE-OR elements, respectively.
EFFECT: ensured implementation by means of constant configuration of any of the operations (A+B) mod 3, (A-B) mod 3, wherein A, B ∈ {00,01,10} are two-bit binary numbers set by binary signals.
1 cl, 1 dwg, 1 tbl
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Authors
Dates
2021-10-21—Published
2020-09-24—Filed