FIELD: computing technology.
SUBSTANCE: invention relates to a parallel counter. The counter is comprised of seven EXCLUSIVE-OR elements and two AND elements, wherein the first, second inputs of the ith and the output of the jth EXCLUSIVE-OR elements are connected with the first, second inputs of the ith AND element and the second input of the (j+1)th EXCLUSIVE-OR element, respectively, and the first input of the fourth EXCLUSIVE-OR element is connected with the fifth input of the parallel unit counter, wherein additionally introduced thereto are five majority elements, the (j-2)th input of the kth majority element, the second input and the output of the first AND element are connected with the (j-2)th input of the (k+2)th, the input of the seventh and the first input of the second EXCLUSIVE-OR elements, respectively, and the output of the (j-2)th, the output of the (i+3)th majority elements and the outputs of the sixth, ith EXCLUSIVE-OR elements are connected with the (6-j)th input of the seventh, the ith input of the ith EXCLUSIVE-OR elements and the first, (i+1)th outputs of the parallel unit counter, respectively, the (j-2)th, fourth, sixth, seventh, eighth, ninth and fourth inputs whereof are connected with the (6-j)th input of the third, the third input of the fourth, the third, first inputs of the fifth, the third, first inputs of the sixth EXCLUSIVE-OR elements and the output of the second AND element, respectively.
EFFECT: simplified configuration of a parallel unit counter.
1 cl, 1 dwg, 3 tbl
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Authors
Dates
2021-11-23—Published
2020-10-28—Filed