FIELD: data encryption.
SUBSTANCE: disclosed is a symmetrical data encryption apparatus (SDEA) implemented in the form of a system on chip (SOC), including a central processing unit, an internal switching unit, a frontend controller, a multiplexing unit, and an encryption apparatus including: a direct memory access controller, a computing module, a pseudo-random number generator, a timer, a general purpose register for storing the substitution table (ST GPR), a general purpose register for storing the secret encryption keys (SEK GPR), an additional SEK GPR, and a control unit; wherein the CPU is connected by a data bus (DB) with the internal switching unit and by a configuration interface with the direct memory access controller and the control unit; the internal switching unit is connected by data buses with the direct memory access controller, and by data buses with the memory access controller and the frontend controller; the memory access controller is connected with the memory, and the frontend controller is connected via a multiplexed data bus with the multiplexing unit also receiving signals from the control unit via the control bus by the multiplexing unit and having multiplexed frontend buses entering the SOC output; the computing module is interconnected with the ST GPR, SEK GPR, and additional SEK GPR, control unit, and receives signals from the direct memory access controller via a DB and the pseudo-random number generator; the control unit sends signals to the ST GPR, SEK GPR, and additional SEK GPR via a DB to the direct memory access controller and is interconnected with the timer.
EFFECT: ensured strong authentication between subscribers in the encryption procedure.
3 cl, 6 dwg
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Authors
Dates
2022-01-28—Published
2020-05-14—Filed