FIELD: computing technology.
SUBSTANCE: invention relates to architectures of a digital signal processor. Programmable digital signal processor comprises a digital filter, a shift register search table, a filter memory, and a finite-state machine. The digital filter comprises a multiplier and an accumulating adder. The multiplier receives input data from the filter memory and the shift register search table. The shift register search table contains a shift register containing triggers. The finite-state machine provides addressing values to the shift register search table and the filter memory. The addressing values contain the same address for the shift register search table and the filter memory.
EFFECT: provided DSP architecture providing more unified functionality while maintaining a high degree of versatility.
9 cl, 8 dwg
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Authors
Dates
2022-04-11—Published
2019-06-19—Filed