FIELD: computer engineering.
SUBSTANCE: increase of the throughput of the processor is achieved due to the fact that the processor may contain cells for processing a matrix of N×N data elements and a vector of N×1 data elements. The VRF may, in response to a write instruction, store N data elements in the multiport memory and, during each cycle of P clock cycles, provide N data elements to each of the P input interface circuits of the multiport memory containing an input path configured to transmit L data elements in parallel. During each cycle of the P clock cycles, the multiport memory may be configured to receive N data elements via at least one selected of the P input interface circuits. The VRF may include output interface circuitry for providing N data elements in response to a read instruction.
EFFECT: increasing the throughput of the processor.
15 cl, 5 dwg, 3 tbl
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Authors
Dates
2023-05-12—Published
2019-04-06—Filed