FIELD: computing technology.
SUBSTANCE: technical solution relates to the field of microprocessor computing. The technical result is achieved by the scalar-vector processor containing a reduction unit connected with the scalar and vector channels of the processor and implementing the functions of interaction thereof in operations where the scalar channel forms and/or utilises the scalar required and/or formed by the vector channel of the processor; the reduction unit also executes operations on the vector in general, i.e., permutation operations (shuffle), LUT transformations, and histogram calculations; the scalar and vector channels of the processor are additionally combined by an annular bus enabling data exchange thereon simultaneously with the execution of computational operations in the scalar and vector channels of the processor and in the reduction unit.
EFFECT: increase in the operation speed and the volume of processed data due to the parallel scalar and vector calculations.
44 cl, 7 dwg, 20 tbl
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Authors
Dates
2022-10-11—Published
2021-11-03—Filed