FIELD: digital circuitry.
SUBSTANCE: invention relates to digital circuitry, automation and industrial electronics and, in particular, can be used in computer technology units based on D flip-flops. Trigger asynchronous D flip-flop on field-effect transistors additionally contains five resistors and a reference constant voltage source. The first resistor is connected between the positive terminal of the DC supply voltage and the common terminal of the drains of the first and third field-effect transistors. The second resistor is connected between the "ground" and the common output of the sources and substrates of the first and second field-effect transistors. The third resistor is connected between the drain of the second FET and the common terminal of the first resistor and the positive terminal of the DC supply voltage. One of the terminals of the fourth resistor is connected to the common terminal of the source and substrate of the third field-effect transistor. One of the terminals of the fifth resistor is connected to the drain of the fourth field effect transistor and their common terminal is connected to the gate of the third field effect transistor. The free terminals of the fourth and fifth resistors are connected together and their common terminal forms the Q flip-flop output relative to ground. The gate of the fourth transistor is connected to the common terminal of the first resistor, drains of the first and third field-effect transistors. The common terminal of the source and substrate of the fourth field-effect transistor is connected to the common terminal of the third resistor and the drain of the second transistor. The negative output of the reference DC voltage source is grounded, its positive output is connected to the gate of the second field-effect transistor.
EFFECT: increasing the load capacity of the trigger asynchronous D flip-flop on field-effect transistors.
1 cl, 2 dwg
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