FIELD: computer technology.
SUBSTANCE: implementation of the functional units of the device, which enables reduction of the number of logical elements contained in them and the length of the logic signal propagation chains from inputs to outputs, as well as to compact the physical CMOS transistor structure of the error address decoder and correction circuit.
EFFECT: increased speed and fault resistance of the device.
3 cl, 10 dwg, 6 tbl
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Authors
Dates
2023-07-28—Published
2023-01-13—Filed