FIELD: electricity.
SUBSTANCE: invention relates to a control method, a semiconductor memory device and an electronic device. Method includes: decoding a third operand in a third mode register (MR) and a fourth operand in a first MR; control, in response to the fact that the semiconductor memory device is in a given test mode, in the case when the third operand satisfies the first decoding condition, the impedance of the pin for the Data Mask Pin (DM) as the first value; or control, in the case where the third operand satisfies the second decoding condition, the impedance of the DM pin as the second value corresponding to the fourth operand; wherein the third operand is configured to indicate whether the DM pin is a test object in a given test mode, and the fourth operand is configured to indicate whether the DM pin is involved.
EFFECT: possibility of checking impedance of a pin for a data mask in a given test mode in order to avoid circuit processing errors.
25 cl, 5 tbl, 15 dwg
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Authors
Dates
2024-09-17—Published
2022-05-19—Filed