FIELD: electrical engineering.
SUBSTANCE: invention relates to semiconductor storage devices. Disclosed is a method of controlling a semiconductor memory device, a semiconductor memory device and an electronic device comprising a semiconductor memory device. Disclosed is an impedance control strategy for a data mask pin in a given test mode so that the impedance of the data mask pin in a given test mode can be set. Determined is the ratio between the control signal configured to control whether to use the pin for the data mask in the double data rate synchronous RAM, and a control signal configured to control whether the pin for the data mask is a test object in the output signal generator packet test mode (PODTM mode).
EFFECT: invention enables to check the impedance of the pin for the data mask in a given test mode in order to prevent errors in data processing by the circuit.
16 cl, 12 dwg
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