FIELD: computer engineering.
SUBSTANCE: technical result is achieved by the fact that in the claimed solution a hybrid computer system is provided, comprising a central processor with a system bus, a two-dimensional matrix of operational bits of the converting FCFS-register, associative memory, operating synchronously and combined with a single FCFS-register channel for controlling input and storing bit instructions: subprocessor channel of streaming data processing as part of a pre-, co- and postprocessor, interacting with each other through a software-reconfigurable loopback bus, interacting with central processing unit through its system bus, including arithmetic logic devices, control devices, interface devices, address devices, diagnostic devices, command registers, delay elements, switches, with possibility of program-configuring and/or reconfiguring the computing surface for non-cyclic transformations of the connected oriented surface of genus 0 and for cyclic transformations of the connected oriented surface of genus 1 and higher.
EFFECT: creation of conflict-free multithreading processing of instructions and data.
1 cl, 4 dwg
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Authors
Dates
2024-11-14—Published
2023-11-02—Filed