FIELD: computer engineering. SUBSTANCE: device has four input registers, two registers, generator of code for integer shift, integer normalizing unit, integer shift/sign-inversion unit, unit for generation of integer shift codes, control unit, two output registers. Two generators of exponent of integers, additional generator of code for integer shift, additional integer normalizing unit, additional integer shift/sign-inversion unit, two generators of signal for integer round- off, two additional registers are introduced to accomplish the goal of invention. EFFECT: increased speed of exponent matching due to decreased number of logical levels during conversion form integer to real and due to increased speed of shift code access. 2 cl, 4 dwg
Title | Year | Author | Number |
---|---|---|---|
ADDER | 1991 |
|
RU2006915C1 |
DEVICE FOR NORMALIZING AND ROUNDING OFF REAL NUMBERS | 1992 |
|
RU2018921C1 |
COMPUTING UNIT | 1992 |
|
RU2035064C1 |
ADDER | 0 |
|
SU1837281A1 |
COMPUTING SYSTEM | 1989 |
|
RU2028663C1 |
ADDER OF EXPONENTS | 0 |
|
SU1837282A1 |
MEMORY CONTROL UNIT | 1991 |
|
RU2010318C1 |
SUBROUTINE CALL UNIT | 1990 |
|
RU2009538C1 |
BUFFER MEMORY CONTROL UNIT | 1990 |
|
RU2010317C1 |
OPTICAL ADDER | 1993 |
|
RU2079872C1 |
Authors
Dates
1994-01-30—Published
1992-06-30—Filed