FIELD: computer engineering. SUBSTANCE: device has two input registers, decoder, input exponent adder, adder, three registers, result normalization unit, correction exponent generator, normalization control unit, output exponent adder, shift unit. Additional mantissa shift unit, two commutators, three additional registers, shift unit, sign-inversion signal generator are introduced to accomplish the goal of invention. EFFECT: increased speed due to conveyer organization which provides separation of addition of high and low parts of double precision real numbers. 2 cl, 5 dwg
Title | Year | Author | Number |
---|---|---|---|
DEVICE FOR EXPONENT MATCHING OF OPERANDS | 1992 |
|
RU2006910C1 |
DEVICE FOR NORMALIZING AND ROUNDING OFF REAL NUMBERS | 1992 |
|
RU2018921C1 |
COMPUTING UNIT | 1992 |
|
RU2035064C1 |
ADDER | 0 |
|
SU1837281A1 |
COMPUTING SYSTEM | 1989 |
|
RU2028663C1 |
MEMORY CONTROL UNIT | 1991 |
|
RU2010318C1 |
PIPELINE PROCESSOR UNIT | 1992 |
|
RU2032215C1 |
BUFFER MEMORY CONTROL UNIT | 1990 |
|
RU2010317C1 |
CENTRAL PROCESSOR | 0 |
|
SU1804645A3 |
ADDER OF EXPONENTS | 0 |
|
SU1837282A1 |
Authors
Dates
1994-01-30—Published
1991-12-27—Filed