FIELD: computer technology. SUBSTANCE: address former has input key 1 which has information input D to be address input A of address former, control unit 12 which has output connected with control input of input switch 1, memory cell which has information input connected with output Z of input switch 1, two adjusting switches 9 which have information inputs connected with power bus VCC and mode selection signal former 13 which has input 14 connected with the first input of control circuit 12 (input 14 has to be input of mode selection signal former). The fourth input 17 of control circuit 12 is connected with the first input 18 of mode selection signal former 13. The second input 19 of former 13 is with connected with control inputs 20 of adjusting switches 9. The third input 21 21 of former 13 is connected with control input 22 of memory cell 2. Outputs 23 and 24 of memory cell 2 are connected with the second and the third outputs 25 and 26 correspondingly of control circuit 12. Memory cell is connected with outputs 10 and 11 of adjusting switches 9 and have to direct and inverting outputs of address former. EFFECT: improved reliability of address former due to reduction of consumption current. 3 cl, 7 dwg
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Authors
Dates
1994-03-30—Published
1991-09-25—Filed