FIELD: automatics and computer engineering. SUBSTANCE: device has decoders 3, 4, four groups of OR gates 5, 6, 12, 13, four OR gates 7, 8, 14, 15, two modulo 2 adders 9, 16, AND gates 30-33 from first to fourth, three switching units 17-19, four encoders 20-23, five units 11, 24-27 of AND gates, unit 28 of OR gates. The result of modulo multiplying operation is determined from partial moduli m1 and m2 (m1·m2 ≥ m,, where m is a modulus of operation with further conversion of operation result into a modulo m binary code. EFFECT: enhanced efficiency. 6 tbl, 1 dwg
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Authors
Dates
1994-08-30—Published
1991-07-08—Filed