FIELD: microelectronics. SUBSTANCE: insulating layer of thermal silicon dioxide is formed on surface of substrate of first polarity of conductivity with pockets of second polarity of conductivity; all source and drain regions and isolating regions of MOS transistors of both polarities are opened simultaneously; auxiliary silicon dioxide layer of thickness at least 0.3 of that of insulating layer is grown on surfaces of open regions; source and drain regions and n-type isolating regions are photoengraved by using mask with windows of greater size than openings in insulating layer; then n-type dope alloying and accelerated low-temperature oxidation of n-type alloyed regions in wet environment is carried out, sources, drains, and isolating p-type regions are alloyed through auxiliary layer, whereupon insulating and auxiliary layers are photoengraved while opening regions for gate and contacts; gate dielectric and gate electrode are formed. EFFECT: facilitated procedure. 4 cl, 4 dwg
