CMOS ARRAY CHIP MANUFACTURING PROCESS Russian patent published in 1998 - IPC

FIELD: microelectronics; digital, analog, and analog/digital integrated circuits. SUBSTANCE: process for manufacturing CMOS integrated circuit array chips with polysilicon gates self- combined with sources, drains, and polysilicon interconnections of first level includes formation of layers of field-effect and gate insulation, polysilicon gates, and sources self- combined with gates, MOS transistor drains, layers of polysilicon and metal interconnections separated by interlayer insulation on semiconductor substrate surface; upon formation of gate polysilicon layer, windows are photoengraved in gate polysilicon for sources and drains at the same time forming circuits of gates corresponding to MOS transistors, then regions of sources and drains of n and p types self-combined with gate are produced by ion doping whereupon polysilicon interconnections are photoengraved; figures are made in interconnection pattern covering polysilicon gates already made by more than maximal separation of interconnection layer relative to n and p source and drain layers. EFFECT: reduced manufacturing cost. 6 cl, 9 dwg