MANUFACTURING PROCESS FOR MOS LARGE-SCALE INTEGRATED CIRCUITS WITH PRECISION POLYSILICON RESISTORS Russian patent published in 1997 - IPC

FIELD: analog and analog-digital integrated circuits. SUBSTANCE: process involves formation of highly doped gate polysilicon layer on semiconductor substrate covered with insulation, removal of gate polysilicon layer from areas of resistors, deposition of resistive polysilicon layer and its doping, formation of gate and resistor patterns by photoengraving of polysilicon layers, thermal oxidizing of resistive polysilicon in wet medium, and formation of sources, drains of MOS transistors, and evaporation of connections; upon formation of highly doped gate polysilicon layer, the latter is subjected to photoengraving and removed at points of location of resistive sections with gate polysilicon left at points of location of resistor contact pads; resistive polysilicon layer is deposited and doped with ion-doped phosphor or arsenium at rate of 100-500 mcC/sq.cm; pattern of polysilicon gates and resistors is formed by photoengraving and joint etching of gate and resistor polysilicon layers; resistive polysilicon is at least once thermally oxidized in wet medium at 800 to 950 C until it is oxidized through 0.4-0.7 of its original thickness. EFFECT: facilitated manufacture. 4 cl, 3 dwg