MEMORY UNIT Russian patent published in 1998 - IPC

FIELD: electronic equipment, in particular, synchronous memory units. SUBSTANCE: each decoder 3 and 4 for row access has one additional prohibition input which is connected to device synchronization input 8. This results in possibility to lock outputs of decoders 3 and 4 for transition time of input address and data signals in order to prevent false writing. In addition device has memory registers 1, device access inputs 2 and input D flip-flops 9. EFFECT: increased reliability in writing mode when synchronization in alternation of signals at address and information inputs 5, 6 and 7 is broken. 1 dwg