FIELD: digital microelectronics; emitter-coupled logic integrated circuits. SUBSTANCE: newly introduced in cell are first and second pairs of controlled transistors. Emitters of transistors of main and additional flip-flops are combined. Leads of first and second resistors are connected to plus terminal of voltage supply. Other leads function as direct and inverted sync outputs of cell. Bases of first and second control transistors are combined and function as direct and inverted sync inputs of cell. Combined collectors of first and second transistors of additional flip-flop function as direct output of cell. Combined collectors of third and fourth transistors of additional flip- flop function as inverted output of cell. Input levels of sync signals and output logic levels of data signals of synchronous flip-flop cell are matched which is required for setting up stages of such circuits. EFFECT: reduced number of current supplies, reduced power requirement, improved reliability of circuit. 2 dwg
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Authors
Dates
1998-09-27—Published
1997-07-29—Filed