ENERGY EFFICIENT LOW VOLTAGE CMOS TRIGGER Russian patent published in 2017 - IPC H03K3/00 

FIELD: electricity.

SUBSTANCE: invention offers energy efficient low voltage CMOS trigger including the input and output cascades, each of which is built on two identical CMOS inverters, and also has a key NMOS transistor connecting the output of inverters which is "common" with a general power bus, wherein the circuit additionally includes third and fourth key pMOS transistors, and the source of third key pMOS transistor is connected to the positive supply bus, drain thereof - to the joint power supply inputs of the first and second input cascade inverters, while its gate is connected to inverted trigger synchronization input; the fourth key pMOS transistor's source is connected to the positive supply bus, and drain is connected to joint supply outputs of the first and second output cascade inverters, while its gate is connected to direct trigger synchronisation input.

EFFECT: expansion of the range of allowable supply voltages, improving performance and reducing power consumption of synchronous triggers.

5 dwg