FIELD: pulse engineering; automatic-control and instrumentation engineering. SUBSTANCE: proposed device has frequency standard 3; first pulse counter 6 whose bit outputs are connected to address inputs of memory unit 7, outputs of the latter being connected to data inputs of second pulse counter 8; OR gate 9 whose first input is connected to first input bus 2. Novelty is introduction of third pulse counter 5 and shift register 4 in device; output of frequency standard 3 is connected to complementing input of third pulse counter 5 and to clock input of shift register 4 whose output is connected to output bus 10; second input of OR gate 9 is connected to borrow output of second pulse counter 8 and to write input of shift register 4 and output, to complementing input of first pulse counter 6 and to write input of second pulse counter 8 whose complementing input is connected to carry output of third pulse counter 5; reset inputs of shift register 4, first and second pulse counters 6 and 5 are connected to first input bus 2 and second input bus 1 is connected to data inputs of shift register 4. EFFECT: reduced software volume in shaping short pulses of high relative pulse duration. 1 dwg
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Authors
Dates
2001-06-27—Published
2000-04-05—Filed