FIELD: computer engineering. SUBSTANCE: device designed to execute operations concerned with reception and conversion of self-synchronizing serial binary code in a number of code lengths into parallel-serial code including detection of information error and bit timing failure has receiver/decoder, shift register, pause detector, modulo two check-up component, two flip- flops, up counter, and control unit. Device incorporates provision for receiving and converting input codes in a number of code lengths and their output in byte form in parallel-serial code accompanied by byte number code and byte ready signal and its synchronization, as well as for shaping device serviceability check signal (bit synchronization failure and operation data error), and also for shaping operation result ready signal with aid of program threshold pause detection. EFFECT: enlarged functional capabilities. 3 dwg
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Authors
Dates
2003-04-10—Published
2001-05-22—Filed