FIELD: computer engineering; information processing systems. SUBSTANCE: device has coordinate switch, scalar instruction buffer memory unit, buffer data memory unit, scalar operational units, vector registers, vector instruction buffer memory unit, vector operational units, parallel memory buses, random-access memory units, input/output buses, data input/output units, data availability memory units, data availability logic circuits, engagement register, logic engagement circuit, information bus, chain interface, functional parameter buffer memory unit, and stack memory. Proposed device provides for implementing neuron-network problems and their concurrent solution due to specific network architecture. EFFECT: enlarged functional capabilities; enhanced speed of computing process. 1 dwg, 2 tbl
Title | Year | Author | Number |
---|---|---|---|
NEURO-NET DISCONTINUOUS OPERATION DEVICE | 2003 |
|
RU2250501C2 |
DATA PROCESSING DEVICE | 2000 |
|
RU2179739C2 |
NEURAL NETWORK OPERATIONAL DEVICE | 2008 |
|
RU2394274C2 |
PARALLEL INFORMATION PROCESSING DEVICE | 2008 |
|
RU2379751C2 |
DEVICE FOR INFORMATION PROCESSING | 2008 |
|
RU2373568C1 |
INFORMATION PROCESSING DEVICE | 2006 |
|
RU2331923C2 |
METHOD FOR PROCESSING INFORMATION IN NEURON NETWORKS | 2004 |
|
RU2263964C1 |
MULTIPROCESSOR COMPUTER SYSTEM | 0 |
|
SU1168960A1 |
PIPELINE PROCESSOR UNIT | 1992 |
|
RU2032215C1 |
COMPUTING SYSTEM | 0 |
|
SU1777148A1 |
Authors
Dates
2001-12-10—Published
2000-05-06—Filed