FIELD: physics; computer engineering.
SUBSTANCE: invention relates to computer engineering and can be used in designing discrete information processing systems. This outcome is achieved due to provision of equiprobable servicing of operational units through a mechanism for cyclic change of priorities. The parallel information processing device has a ring bus for transmitting instruction packets, local data memory units, local data-ready memory, local instruction memory, local logic-in memory, which form local instruction packet memory, operational units, engagement triggers, data packet bus, data input and output units, data stack memory unit, a bus for transmitting result packets, results local stack memory units, priority circuit with cyclic change of priorities, comparator circuits, input locking devices, each formed by an address register and a data register, gate units, address bus.
EFFECT: increased efficiency of the device.
2 cl, 2 dwg
Title | Year | Author | Number |
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DEVICE FOR INFORMATION PROCESSING | 2008 |
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RU2373568C1 |
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NEURAL NETWORK OPERATIONAL DEVICE | 2008 |
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DATA PROCESSING DEVICE | 2000 |
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NEURO-NET DISCONTINUOUS OPERATION DEVICE | 2003 |
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DIGITAL INFORMATION PROCESSING DEVICE | 2000 |
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METHOD FOR PROCESSING INFORMATION IN NEURON NETWORKS | 2004 |
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LOGIC STORING DEVICE | 0 |
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Authors
Dates
2010-01-20—Published
2008-03-24—Filed