FIELD: information technology.
SUBSTANCE: neural network operational device has a first ring bus for transmitting instruction packets, local data memory units, local data availability memory, local instruction memory and local logic-in memory, which form local instruction packet memory units, operational units, engaged trigger circuits, a second ring bus for transmitting data packets, data input and output units, local results stacks, parallel input/output registers with availability bits, NAND logic element and the same number of inhibition gates as operational units, where the parallel data packet registers with availability bits and parallel input/output registers with availability bits form the second ring bus.
EFFECT: higher efficiency of the device owing to possibility of simultaneous transmission of instruction packets through parallel registers and shift of instruction packets through the ring bus.
2 cl, 2 dwg
Title | Year | Author | Number |
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DEVICE FOR INFORMATION PROCESSING | 2008 |
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RU2373568C1 |
PARALLEL INFORMATION PROCESSING DEVICE | 2008 |
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RU2379751C2 |
NEURO-NET DISCONTINUOUS OPERATION DEVICE | 2003 |
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RU2250501C2 |
METHOD FOR PROCESSING INFORMATION IN NEURON NETWORKS | 2004 |
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RU2263964C1 |
INFORMATION PROCESSING DEVICE | 2006 |
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RU2331923C2 |
DIGITAL INFORMATION PROCESSING DEVICE | 2000 |
|
RU2176815C1 |
DATA PROCESSING DEVICE | 2000 |
|
RU2179739C2 |
LOGIC STORAGE | 0 |
|
SU674101A2 |
COMPUTING SYSTEM | 0 |
|
SU692400A1 |
PARALLEL COMPUTING ARCHITECTURE | 2016 |
|
RU2644535C2 |
Authors
Dates
2010-07-10—Published
2008-06-02—Filed