FIELD: digital computer engineering; complementary metal-dielectric-semiconductor integrated circuits for arithmetic and logical devices. SUBSTANCE: introduced in device are additional inverter 3 and p-type clock transistor 2 coupled with this inverter and inserted between power bus 34 and plus power terminals 53 of inverters 3 and 6 which are clocked devices using gates of p-type inverter transistors as logic inputs 48 and 49 connected to outputs 36 and 38 of logic unit 17 as well as n-type inverter transistors functioning as clock input 50 connected to output of additional inverter 3; newly introduced in logic unit 12 of each adder stage are also two n-type transistors 31 and 32 together with new connections between key circuits in logic unit 12 built around n- type transistors. EFFECT: enhanced speed. 1 dwg
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