CASCADE PARAPHASE LOGIC UNIT Russian patent published in 2009 - IPC H03K19/948 

FIELD: physics, computer facilities.

SUBSTANCE: invention concerns field of computer facilities and can be used in MDT integrated circuits at embodying of logic units. The device contains in each stage first (1) and second (2) CMDT inverted rectifiers included under the plan of the trigger, input (3) and output (4) timing devices, first (5) and second (6) transistors of dump of n-type and logic block (7) containing some of key chains, (8) between exits (8) both (9) stages and ground busbar (12). Input timing device (3) is executed under the inverted rectifier plan which inlet is connected to clock inlet (13) stages and joined to shutters of transistors of dump (5) and (6) n-types, and its exit (17) joined to plug (10) positive CMDT feeding of the inverted rectifiers which exits are joined to corresponding exits (8) and (9) stages and with shutters of parallelly included transistors of n-type (20) and (21) output timing device (4), shutter of transistor (18) which r-types is connected to plug (10), and the exit is clock exit (19) stages. Logic block (7), contains the key chains executed from consistently joined transistors of n-type which shutters are connected to paraphase logic inlets (22) stages in such a manner that only one key chain is normally closed, and all others - are normally unlocked.

EFFECT: device simplification.

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