FIELD: computer engineering, possible use for receiving digital differential signal of serial self-syncing RZ code with transformation to output signal of serial binary code and asynchronous signal outputs bit synchronization with following interference-resistant generation of output bit synchronization signals, beginning of pause and pause with aid of input continuous series of clock impulses.
SUBSTANCE: device contains transformer-receiver, binary counter, AND elements, AND-NOT element, OR-NOT elements, digital comparator, triggers, two-bit shift register, inputs of first and second components of digital differential signal, starting clearance input, clock input, logical "1" input, code inputs for pause detection threshold and for programming position of beginning of bit synchronization signal relatively to beginning of asynchronous bit synchronization signal, four outputs.
EFFECT: expanded functional capabilities of decoder and increased resistance thereof to interference.
1 dwg
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Authors
Dates
2007-01-10—Published
2005-05-27—Filed