FIELD: physics.
SUBSTANCE: proposed invention allows for complex extension of decoder performance and provision of its noise immunity by means of continuous series of input clock pulses IC due to noise immune shaping of output timed signal OZ of serial binary code and output synchrosignals of bit timing OCZ, pause OPZ and pause origin OPC for code RZ or "BTK" by rejecting filtration of asynchronous three-level coded signal Z(1:O) as interference at each signal change duration not exceeding threshold duration P·Tic for P≥1, where P is threshold number, Tic is clock pulse IC period duration. The decoder contains triggers (1-4), receiving transmitter (5), input (6) of three-level coded signals, OR-NOT components (7-9), synchronous counter (10), OR components (11-13), delay component (14), AND components (15-16), Excluding OR components (17-18), register (19), comparator (20), AND-NOT components (21-24), input (25) of decoded three-level coded signal selection, clock input (26), code input (27) of pause detection threshold, code input (28) synchrosignal detection threshold, the first output, which is an output of trigger (1) and timed signal OZ of serial binary code, and the second, third and fourth outputs which are outputs of component (15), trigger (3) and component (9) and outputs of synchrosignals of bit timing OCZ, pause OPZ and pause origin OPC, respectively.
EFFECT: extended performances of decoder and its noise immunity.
1 dwg
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Authors
Dates
2008-09-10—Published
2007-06-04—Filed