FIELD: electrical communications; frame synchronization of messages in digital data transfer systems.
SUBSTANCE: proposed device for selecting frame-synchronization marker has shift register, comparison gate with reference marker combination and coincidence code analysis unit, first AND circuit, first masking sequence generator, marker character generator, coincidence code computing unit, second AND circuit, second masking sequence generator, and threshold unit. Shift register unit functions as input of frame-synchronization marker selecting device; shift register has aggregate of series-connected memory items; output of second group of memory items is connected to input of comparison gate having reference marker combination. Output of comparison gate having reference marker combination is connected to input of first and second masking sequence generators, to input of marker character generators, and to synchronization output of device; output of marker character generator is connected to input of coincidence code computing unit whose output is connected to input of coincidence code analyzing unit; output of the latter is connected to input of threshold unit whose output functions as data output of frame-synchronization marker selecting device.
EFFECT: enhanced noise immunity.
1 cl, 1 dwg
Title | Year | Author | Number |
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0 |
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Authors
Dates
2006-03-10—Published
2004-09-13—Filed