FIELD: digital computer engineering; computer processor devices and digital automated devices.
SUBSTANCE: proposed method includes consecutive execution during the first time step of operations of reading the second summand, modulo-two sum operation, writing the result to the first RS-trigger and forming the step-by-step and ripple carry. During the second time step the second modulo-two sum operation is executed with its result written to the second RS-trigger of current or lower order bit. The device which implements this method consists of nine AND elements, five OR elements, two RS-triggers, two half-adders and eight control inputs for every bit.
EFFECT: increased processing speed, less equipment, increased list of available operations.
2 cl, 3 dwg
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Authors
Dates
2006-11-20—Published
2005-06-27—Filed