FIELD: computer engineering, possible use in processors of computers and digital automatics devices.
SUBSTANCE: result is achieved because device in each bit contains logical elements AND 1-11, two RS-triggers 12,13, logical elements OR 14-17, logical elements NOT 18-20, nine control inputs, information input and output.
EFFECT: increased speed of execution of operations, expanded list of realized operations at minimal equipment costs.
1 dwg, 1 tbl
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RU2505850C2 |
| METHOD AND SYSTEM OF EXECUTING CALCULATION OPERATIONS WITH MINIMAL COST OF EQUIPMENT | 2005 |
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RU2287849C1 |
| METHOD AND DEVICE FOR ADDING | 2005 |
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RU2308073C2 |
| COUNTER-TYPE ADDER | 2005 |
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RU2288501C1 |
| METHODS OF EXECUTING COMPUTATIONAL PRIMITIVES AND DEVICE THEREFOR | 2013 |
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RU2553221C2 |
| METHOD AND APPARATUS FOR MULTIPLYING BINARY CODED DECIMAL | 2009 |
|
RU2410745C1 |
| COMBINATION TYPE ADDER | 2004 |
|
RU2275676C1 |
| METHOD AND DEVICE FOR ADDING BINARY CODES | 2013 |
|
RU2537046C2 |
| ACCUMULATING TYPE ADDER | 2003 |
|
RU2269153C2 |
| BINARY CODED DECIMAL SUMMATION METHOD AND DEVICE | 2007 |
|
RU2402803C2 |
Authors
Dates
2007-03-20—Published
2005-05-17—Filed