FIELD: radio engineering and communications for amplifying two different signals in miscellaneous analog integrated circuits (such as those of operational amplifiers and comparators).
SUBSTANCE: proposed differential amplifier has first input differential stage 1 with first current-stabilizing two-terminal network 2 whose first lead is connected to emitters of input n-p-n transistors, bases of the latter being connected to differential-amplifier inputs 5 and 6; second differential stage 7 with second current-stabilizing two-terminal network 8 whose first lead is connected to emitters of input p-n-p transistors 9 and 10, bases of the latter being coupled with differential-amplifier inputs 5 and 6; output stage built around p-n-p and n-p-n output transistors 11 and 12, respectively, whose collectors are connected to load 13, bases, to respective positive and negative bias voltage supplies 14 and 15, respectively, emitter of transistor 11 being coupled through two-terminal network 16 with bus of power supply 17 and with collector of transistor 4; emitter of transistor 12 is connected through two-terminal network 18 to bus of power supply 19 and to collector of transistor 10. Newly introduced in differential amplifier are p-n-p and n-p-n transistors 20 and 21, respectively, whose collectors are connected to load 13, bases, to respective bias-voltage supplies 14 and 15; emitter of transistor 20 is connected to bus of power supply 17 through two-terminal network 22 and to second lead of current-stabilizing two-terminal network 8; emitter of second transistor 21 is connected to bus of power supply 19 through two-terminal network 23 and to second lead of two-terminal network 2.
EFFECT: enhanced common-mode rejection ratio.
2 cl, 7 dwg
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Authors
Dates
2008-03-10—Published
2006-06-19—Filed