METHOD OF DETECTING AND REMOVING FAULTS IN CONVERTER CIRCUIT FOR THREE LEVEL VOLTAGE COMMUTATION Russian patent published in 2009 - IPC H02H7/122 

FIELD: electricity.

SUBSTANCE: proposed is a method of detecting and removing faults in a converter circuit for three level voltage commutation with the converter circuit containing a converter subsystem per each phase (R, S, T). Detected is the upper (A) or the lower (B) fault current circuit of the converter subsystem (1) with the upper fault current circuit (A) passing through the first (S1), the second (S2), the third (S3) and the sixth (S6) semiconductor power switches of the converter subsystem (1) or through the first (S1) and the fifth (S5) semiconductor power switches of the converter subsystem (1) and the lower fault current circuit (B) passing through the second (S2), the third (S3), the fourth (S4) and the fifth (S5) semiconductor power switches of the converter subsystem (1) or through the fourth (S4) and the sixth (S6) semiconductor power switches of the converter subsystem (1), the semiconductor power switches (S1, S2, S3, S4, S5, S6) closure being actuated by sequences of faulty commutations. To provide for avoidance of short circuiting with all the phases of the converter circuit as well as for the latter's reliable operability under fault conditions in case of the upper (A) or the lower (B) fault current circuit having been detected after a sequence of faulty commutations the commutation status of each semiconductor switch (S1, S2, S3, S4, S5, S6) occurring during detection is registered the first thing. If the upper fault current circuit (A) has been detected the first (S1) and the third (S3) semiconductor power switches are cut off successively; in case of the lower fault current circuit (B) detection the fourth semiconductor power switch (S4) is cut off first followed by the second semiconductor power switch (S2).

EFFECT: enhanced reliability.

10 cl, 8 dwg