FIELD: physics; computer engineering.
SUBSTANCE: present invention relates to methods of caching target addresses of a branch instruction, particularly to improvement of selecting a cache target address with regard to selection of cache branch instruction. A pipeline processor contains instruction cache (iCache), branch target address cache (BTAC) and processing steps, including steps for selecting between iCache and BTAC. Versions of the methods describe operation of the above mentioned processor. To compensate for the number of cycles, required for selecting the branch target address from BTAC, selection from BTAC leads to selection of branch instructions from iCache by a value, related to the number of cycles, required for selection from BTAC.
EFFECT: increased efficiency of processes realised using these methods.
30 cl, 8 dwg
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