FIELD: information technology.
SUBSTANCE: apparatus has a first input which is configured to receive an instruction address, and a second input which is configured to receive predecoded information which describes the instruction address as being related to an implicit subroutine call in a subroutine. In response to the predecoded information, the apparatus also includes an adder configured to add a constant to the instruction address defining a return address, causing the return address to be stored to an explicit subroutine resource, thus, facilitating subsequent branch prediction of a return call instruction.
EFFECT: emulating branch prediction of a subroutine call in order to reduce power and increase pipeline processor utilisation factor.
13 cl, 1 tbl, 7 dwg
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|---|---|---|---|
| MULTIPROCESSOR ARCHITECTURE OPTIMISED FOR FLOWS | 2007 |
|
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| ERROR HANDLING FOR EARLY DECODING THROUGH BRANCH CORRECTION | 2005 |
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| MULTIPROCESSOR ARCHITECTURE OPTIMISED FOR TRAFFIC | 2008 |
|
RU2450339C2 |
| SYSTEMS AND METHODS OF PROCEDURE RETURN ADDRESS CHECKING | 2014 |
|
RU2628163C2 |
| DEBUGGING SCHEME COMPARING PROCESSOR INSTRUCTION SET PROCESSING MODE | 2007 |
|
RU2429525C2 |
| SYSTEMS AND METHODS FOR PREVENTION OF UNAUTHORIZED STACK PIVOTING | 2014 |
|
RU2629442C2 |
| LOADING/MOVING AND COPYING COMMANDS FOR PROCESSOR | 2002 |
|
RU2292581C2 |
| ACTIVE HARDWARE STACK OF THE PROCESSOR | 2013 |
|
RU2530285C1 |
| PRESENTATION OF CYCLE TRANSITIONS IN TRANSITIONS PREHISTORY REGISTER USING MULTIPLE BITS | 2007 |
|
RU2447486C2 |
| METHOD AND SYSTEM FOR CONTROLLING EXECUTION WITHIN COMPUTING ENVIRONMENT | 2012 |
|
RU2577487C2 |
