FIELD: information technology.
SUBSTANCE: invention relates to processors, particularly to a method of reducing power consumption when caching data with write behind by checking the modified bit (GMI), which indicates whether any cache memory element with write behind contains any altered data. The processor includes cache memory having at least one element controlled by a write behind algorithm. In case of cache miss, if the GMI indicates that not any of the cache memory elements with write behind in the given cache memory contains altered data, data extracted from memory are stored in a selected element without preliminary reading by the said element. In cache memory divided into banks, two or more GMI banks can be associated with two or more banks. If there is an n-dimensional set of associated cache memory elements, n GMI sets can be associated with data of n sets.
EFFECT: increased processor efficiency and reduced power consumption.
10 cl, 2 dwg
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